In the current fabrication of large scale integrated circuit, the poly-insulator-poly (PIP) capacitor is widely used. In the popular process of 0.5 μm Mix PIP, a Low Pressure Tetraethyl Orthosilicate (LPTEOS) is commonly used as an intermediate insulating layer. However, the unit capacitance value of this capacitor is only 0.72 fF/μm2, i.e. 0.72×10−15 F/μm2, which has been a factor of restricting the chip integration level; thus the method of fabricating a capacitor with a higher unit capacitance value has become a hotspot of this industry.
Two methods are proposed to improve the capacitance value of the PIP-type capacitor. One is to make the LPTEOS layer with a thickness of about 400 angstroms become thinner, however, the breakdown voltage of the thinner capacitor is significantly lowered, which is unfavorable to the application of the device. The other is to look for another insulation layer structure to replace the conventional LPTEOS layer.
The Oxide-Nitride-Oxide (ONO) capacitor with a high capacitance value has been widely used. FIG. 1 shows a cross-sectional view of the existing ONO capacitor. As shown in FIG. 1, from bottom to top, the ONO capacitor 10 successively includes: a first polycrystalline silicon 11, which is used as the lower conductive plate of the ONO capacitor; an intermediate dielectric layer 12 with a sandwich structure, the intermediate dielectric layer 12 includes: a first oxide layer 121 disposed on the first polycrystalline silicon 11, a nitride layer 122 disposed on the first oxide layer 121, and a second oxide layer 123 disposed on the nitride layer 122; and a second polycrystalline silicon 13, which is used as the upper conductive plate of the ONO capacitor. The unit capacitance value of this type ONO structure capacitor is more than 1.61 fF/μm2, which is an ideal semiconductor capacitor. However, when this type of ONO structure capacitor is applied in the process of the 0.5 μm PIP capacitor or below 0.5 μm, there are some drawbacks, which mainly includes: firstly, the fabrication step of the sandwich structure includes: growing the first oxide layer 121 on the first polycrystalline silicon 11 by dry oxidation. Specifically, the substrate material is placed in a high temperature diffusion furnace at a temperature of 900° C., then a high-purity oxygen gas is introduced, the oxidation lasts for 70 minutes to 90 minutes; then the silicon nitride layer 122 is deposited on the first oxide layer 121 by low pressure chemical vapor deposition method; a deposition temperature is 700° C. to 800° C.; finally, the second oxide layer 123 is grown on the silicon nitride layer 122 by wet oxidation. Specifically, a water vapor is formed by the combustion of high-purity oxygen and hydrogen, and the surface of the silicon nitride oxide 122 is oxidized; a oxidation temperature is 920° C., the oxidation lasts for 100 minute to 140 minutes. It can be seen that a high temperature treatment is needed for fabricating the three layer materials, a large amount of heat will be produced in the whole process, all the devices are suffered from shifting in varying degrees. Secondly, the first polycrystalline silicon 11, used as the lower conductive plate, is usually shared with the gate of the MOS transistor. According to the conventional processing technology of the MOS transistor, a metal layer or a metallized silicon layer is required to be formed on the polysilicon gate layer; the metal layer or the metallized silicon layer easily peels off after being treated in a high temperature for a long time. Take the tungsten silicide as an example, in the condition of introducing of oxygen, the tungsten silicide easily peels off from the polycrystalline silicon when the temperature exceeds 800° C.; accordingly, the quality of the whole device is effected.
Accordingly, developing a capacitor having a high unit capacitance value, and its fabrication can be applied to the 0.5 μm capacitor or below 0.5 μm, is urgently needed to solve the problem.